// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
// Date        : Thu Sep  4 04:02:00 2025
// Host        : localhost.localdomain running 64-bit CentOS Linux release 7.7.1908 (Core)
// Command     : write_verilog -force -mode synth_stub
//               /root/work/project/main_pro/main_pro.srcs/sources_1/ip/clk_1/clk_1_stub.v
// Design      : clk_1
// Purpose     : Stub declaration of top-level module interface
// Device      : xczu2eg-sfvc784-2-i
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_1(clk_o125m, clk_o750m, clk_o250m, clk_o400m, 
  reset, locked, clk_in1_p, clk_in1_n)
/* synthesis syn_black_box black_box_pad_pin="clk_o125m,clk_o750m,clk_o250m,clk_o400m,reset,locked,clk_in1_p,clk_in1_n" */;
  output clk_o125m;
  output clk_o750m;
  output clk_o250m;
  output clk_o400m;
  input reset;
  output locked;
  input clk_in1_p;
  input clk_in1_n;
endmodule
